The high contention rate of the processor bus becomes a performance bottleneck 對(duì)處理器總線的高爭奪率成為性能瓶項(xiàng)。
The numa architecture can increase processor speed without increasing the load on the processor bus Numa體系結(jié)構(gòu)可以在不增加處理器總線負(fù)載的情況下提高處理器速度。
The internal processor bus described in sec . xx is connected to the external processor bus by a set of bus buffers located on the microprocessor integrated circuit Xx節(jié)所描述的內(nèi)部總線通過一組位于微處理器集成電路內(nèi)的總線緩沖器與外部總線連接。
To carry out a fetch , the processor place ( enables ) the binary - coded address of the desired location onto the address line of the external processor bus 為了完成一個(gè)取數(shù)操作,處理器將所需的單元的二進(jìn)制編碼的地址放(使能)在外部處理器的地址線上。